Research Projects
This page contains smaller research projects I have worked on. These involve projects I participated in as a collaboration with another researcher, class projects as a graduate student, or projects at the University of Michigan while an undergrad.
Collaborations at UC Berkeley
ESL Tool Classification
Participants: Douglas Densmore, Alberto Sangiovanni-Vincentelli, Roberto Passerone
Location: UC Berkeley
Description:
A taxonomy for ESL tools and methodologies that combines UC Berkeley’s platform-based design terminologies with Dan Gajski’s Y-chart work. This is timely and necessary because in the ESL world we seem to be building tools without first establishing an appropriate design flow or methodology, thereby creating a lot of confusion. This taxonomy can help stem the tide of confusion. This work culminated with a paper in IEEE Design and Test which is available at the publications page.
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Functional Modeling
Participants: Douglas Densmore, Shinjiro Kakita, Yoshinori Watanabe, Abhijit Davare, Alberto Sangiovanni-Vincentelli
Location: UC Berkeley
Description:
An optimized functional design space exploration method for multimedia applications is proposed. The basis of the method is a way of representing the dependency and the concurrency of an application in a compact form exploiting algebraic operators and expressions. The optimized design process consists of mapping one of the possible expressions in the application space onto a concurrent architecture. We use the Metropolis design framework to demonstrate the effectiveness of the procedure using an FPGA architecture as the target implementation platform. The advantage of using this platform is the availability of models that approximate well the performance of the final implementation when performing the mapping from function to architecture thus yielding a robust design methodology. This work culminated with a paper at ACSD which is available at the publication page.
Class Projects at Berkeley
Layout Aware Technology Mapping - Spring 2002
Participants: Douglas Densmore, Yosinori Watanabe
Location: UC Berkeley
Course: EECS 219B
Description:
Technology mapping is frequently performed without taking into consideration issues often traditionally associated with later stages in the design phase such as wiring congestion, ability to efficiently route, and timing closure. In addition, technology mapping is often tied to single circuit, technology independent decomposition, which limits the possible mappings. This work incorporates the multiple, technology independent, decomposition approach taken by Lehman and Watanabe via their mapping graph encoding and attempt to make it “Layout Aware”. This addition is explored theoretically via a technique called incremental rectangular placement and experimentally via a structural logic synthesis metric termed adhesion. These approaches are evaluated and are found to experimentally produce mixed results which suggest that these techniques have the potential to positively and negatively impact the characteristics of the resultant mappings.
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Communication Based Design of Coherent Memory Systems - Spring 2002
Participants: Douglas Densmore, Donald Chai, Trevor Meyerowitz
Location: UC Berkeley
Course: CS 252
Description:
Communication Based Design (CBD) is rapidly becoming a widely accepted methodology in the world of design and modeling due to its level of abstraction and proposed orthogonalization of concerns. Currently for many application areas, Domain Specific Languages (DSL) are established as a natural way to compose specific systems and protocols. The drawback to using a domain specific language is that the language is often not applicable to some problem areas. The success of Communication Based Design may be determined by how well it is able to exist in both the general purpose and domain specific modeling paradigms. This paper examines this issue via inspection of memory subsystems, particularly those concerned with cache coherence. An evaluation of the viability of Communication Based Design is presented in the context of existing Domain Specific Languages dealing with cache coherence.
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Programming in LegOS - Spring 2002
Participants: Douglas Densmore and Will Plishker
Location: UC Berkeley
Course: EECS 290O
Description:
This project involved developing the software to enable a Lego platform running LegoOS to find an object, pick it up, and return to the starting location. This was done without human interaction using a path coverage algorithm known as boustrophedon decomposition. The code was structured using embedded software design concepts such as time safety, real time requirements, and a rough task scheduling RTOS.
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BAMM: A Framework for Bus and Memory Co-Simulation - Fall 2001
Participants: Doug Densmore, Donald Chai, and Chidamber Kulkarni
Location: UC Berkeley
Course: EECS 244
Description:
In this work we present a framework to simulate bus and memory controller interaction and functionality. This framework, BAMM, is developed to be as flexible as possible and to allow design space exploration as well as rapid simulation. This simulation allows for various configuration details of these controllers to be expressed whereas the majority of simulation environments abstract away these issues. We feel that these details will be of greater consequence in the future and observing their effects will be a valuable development tool.
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A Modeling Framework for Control Fault Tolerant Reactive Systems (CFTRS)- Fall 2001
Participants: Doug Densmore and Shannon Zelinski
Location: UC Berkeley
Course: EECS 249
Description:
This work describes a class of embedded systems defined as Control Fault Tolerant Reactive Systems (CFTRS). We describe a methodology on which to base a CFTRS. We then provide a modeling system framework based on a refinement of abstraction levels in order to design such systems. Within our framework, fault tolerance is based on three principles: fault detection, isolation, and accommodation. It is these principles which are defined in the context of our modeling system which allow us to reflect the concerns and design considerations of such systems. We then present an example of how the CFTRS model can be adapted to an application. In conclusion, the strengths and weaknesses of our system are discussed.
Projects at the University of Michigan
Verilog Simulator of a Dynamically Scheduled, Speculatively Executing Alpha ISA Pipeline - Spring 2001
Participants: Kanak Agarwal, Doug Densmore, Himanshu Kaul, Michael Kontz
Location: University of Michigan, Ann Arbor
Course: EECS 470
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General Purpose Grounds Keeping Device (GPGD) - 16-bit VLSI Microcontroller - Fall 2000
Participants: Douglas Densmore, Irena Gershkovich, Jennifer Pann, Greg Pezda
Location: University of Michigan, Ann Arbor
Course: EECS 427
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Built-In-Self Test (BIST) Implementations: An overview of design tradeoffs - Fall 2000
Participants: Douglas Densmore, John Hayes
Location: University of Michigan, Ann Arbor
Course: EECS 478
Description:
In today’s Integrated Circuits (ICs), Built-In-Self Test (BIST) is becoming increasingly important as designs become more complicated. Keeping the structural fault coverage high while maintaining an acceptable design overhead is of utmost importance. This paper will examine extremes in both design considerations. Pseudorandom Test Pattern Generation (TPG) will be discussed as a low-overhead, decent (perhaps uncertain) fault coverage model, while deterministic TPG will demonstrate a high-overhead, complete-fault coverage model. With these foundations in place as opposite ends of a BIST spectrum, combinations of the two methodologies will be discussed to find an acceptable merger appropriate for today’s designs.